Continued:

Over past two decades, every processor iteration has added more and more transistors to increase integer performance.

Now all integer codes have various offshoots, like in everyday life you may make decisions based on choices. For instance, if you think A happens then you’ll go to the party, but if B happens you’ll not. You make choices of this nature quite a few times in a 24-hour time span.

The processor makes similar decisions and attempts to guess which would be the right way to go. Guessing wrongly turns out to be rather costly in terms of wasted instruction cycles and therefore time taken to "process" the instructions.

To counter this wrong guessing, or to at least minimise its impact, the processor dies are crammed with branch predictors, caches, and predictive cache pre-fetch units. This has no doubt massively increased speeds for single threaded application but it has also led to much higher power consumption (and hence excessive heating) along with an impossibly large number of transistors on the chip.

In the Cell Processor, the idea is to reverse this trend and do away with the single-minded pursuit of single threaded performance. The space saved would be utilised for incorporating more hardware to enable parallel computing. That is, very few of the resources would be dedicated for single thread instructions and most of the hardware is dedicated to parallel processing such as multimedia computing.

The reason for this is simple. Unlike past times, the performance benchmarking is no longer done by office suites and Adobe Photoshop but more by the multimedia and gaming applications.

The other reason, which is prompting manufacturers to look into this kind of a chip, is to take computing beyond number crunching and to use it as an enabler. Future uses of a processor include real-time voice recognition, unstructured search (Google Image) and better physics for AI games.

The Cell Processor is primarily made up of the following:

1. The PowerPC Processing Element (PPE)
2. The Synergistic Processing Elements (SPE)
3. Internal Element Interconnect Bus (EIB)
4. The FlexIO interface
5. Shared Memory Interface Controller

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