Continued:

Cores and Fabrication: Starting with the next generation, all of Intel’s processors will be dual-core, based on the 65nm fabrication process, and despite various rumors to the contrary, they will have an out-of-order execution core, which has been enhanced to process four simultaneous instructions (currently they can only do three). This would obviously mean that more data can be processed at any given time, therefore, the buffers have been enhanced to ensure the processor keeps on getting the data and doesn’t waste precious clock cycles waiting for the system to respond, hopefully making it more efficient than Intel’s Prescott.

Processor Pipelines: In its upcoming chips, Intel has reduced the length of the pipelines from a massive 31 (for P4) to a mere 14 for the new processors. The biggest advantage of a pipeline that is less than half of what its predecessors had would be power efficiency, thus, Intel’s sudden claim of using five times less power than current P4 CPUs seems very reasonable, indeed.

There are certain important things that we can infer from a shorter pipeline. In the simplest of ways, you can think of pipelines as a production line where whatever is being manufactured moves on a conveyer belt and as it moves, at various stages, different operations are performed on it.

The pipeline of a processor is something of this sort. The more operations that need to be performed, the longer it’ll stay in the pipeline (in today’s processors). You can link the length of the pipeline directly to the processor type, that is, whether it is RISC or CISC where RISC is reduced instruction set computer and CISC is complex instruction set computer.

In the early days when computing languages were simple and the requirements were fairly rudimentary, simple instructions were used to get things done efficiently. Since each instruction was basic, it required several instructions to come together to achieve a complex task. As processor technologies progressed and more and more complex instructions were required, RISC gave away CISC, or complex instruction set, computing and now the processors we run are somewhere in between RISC and CISC (but are more RISC than CISC).

Coming back to our pipelines, if we have a mostly RISC computer, then at every stage in the pipeline, the operation performed on it is fairly simple and can be done quickly, which ensures that the data moves along at a ferocious pace which in turn increases the clock speed of the processor.

If you shorten the pipeline length but want the same product at the end of it, then at each stage you need more complex instructions to operate on the data (basically, the data is what flows through a pipeline) which reduces the clock speed as data takes a lot longer to move from one processing stage to the next. However, since the pipeline is smaller, the power savings are huge.

As we mentioned earlier, Intel said earlier that users wouldn’t want to compromise on the speed and thus, it has made the processor core 4 issue, which reduces power consumption and increases overall performance.

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