Continued:

Guessing and Getting Cache Rich: The launch of the Pentium D showcased that Intel processors were sorely lacking in cache-to-cache transfers. Intel will be fixing this by introducing a direct L1 to L1 (from one core to the next) cache transfer mechanism as well as introduce new and/or improved pre-fetch algorithms which will manage data transfer between L1 to L1 and L1 to L2 between and within the same processor core. The L2 cache will be shared between the two cores (as we saw in Yonah) and will also feature a much higher "Effective" (as Intel puts it) bandwidth. What and how that would be done is not clear at the moment.

Along with all the extra cache, L2 bandwidth and prefetch algorithms, Intel is also implementing a speculation solution where the CPU will try to guess which instructions can be processed out of order, that is, which ones can be processed before the instructions sent before them. What that means is that the CPU basically tries to guess if there are dependencies between two instructions and based on certain algorithms, it executes that instruction without waiting for the previous one to finish. If the CPU gets it right, then processing is that much faster as no clock cycles are wasted waiting for the data to come or some other processing to end. This efficiency feature will probably get clearer as we see more and more software getting optimized for dual and perhaps multi-core processors.

Processors and Iterations: The Conroe (desktop) and Merom (mobile) will be available in various iterations, much like the Pentium 4s and Pentium Ms of today. Also, Conroe will be the one available with various sizes of L2 cache to perhaps accommodate versions such as extreme edition. Merom will be available with only one kind of L2 cache.

It’s a natural assumption today that if processors are dual-core, nothing stops them from being multi-core in the future, and Intel is already working towards that. The next generation server processor Woodcrest will be based on two cores but the one after that (to be launched in 2007) have been listed at 2-4 cores, so the processor will probably be quad-core. Obviously, it’s not very clear how Intel will manage to balance out the power consumption on multi-core but that is perhaps a topic for another IDF.

The Intel 955 Extreme Edition (Presler) will probably be the first 65nm processor to hit the market, since Intel has pretty much developed it. And since AMD’s new plant has just begun operating, the world’s second largest chipmaker is a bit behind.

The specs of the processor are out: it’ll operate at 3.46GHz, have two 2MB L2 caches (shared or not is not clear, however we believe shared cache is going to come only from unified architecture of Conroe and the like in H2 ’06), support Intel’s virtualization technology and Hyperthreading.

This is a brief overview of Intel’s future roadmaps for its CPUs. An interesting thing to note here is that Intel’s new architecture, Conroe, Merom and the like will be launched within a year of its 65nm P4s or more appropriately, the 65nm version of its NetBurst architecture. Due to the complete change in platform, it will, in all probability, mean that Conroe won’t be backwards compatible with Presler.

Here’s a list of Intel chips with basic information.

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While Intel has the lead with 65nm at the moment, it would be interesting to see how AMD responds. However, we do have information that AMD is strongly developing 65nm chips as well.