Memory Specifications:

Memory specifications for timings are usualy stated such as 2/2/2/6-11/1T which relate to the values of the CAS/tRCD/tRP/tRAS/CMD.

The last two specifications in 2/2/2/6-11/1T, tRAS and CMD (short for Command) rate, are somewhat complicated and more difficult to understand than simple access and precharge latencies (the first three specifications). The level of misinformation on tRAS and CMD rate are rampant because some memory manufacturers use it for a concept of performance.

CMD Rate and its Misconceptions:

CMD rate is generally used to describe the time from a chip select until a Row Activate Command can be given. The chip select defines the physical bank in which the row is located. In a system running a single, single-sided memory module, there is never a question which bank will be selected since there is only one.

More generally, the CMD Rate is a chipset latency that is not determined by the memory but by the time it takes the chipset to translate the virtual address space into physical memory addresses. Needless to say that higher density system memory with its more addresses will take longer to decode than a single low density module, even if it is double-sided.

Intel has taken care of this problem by simply limiting the number of banks supported per memory channel to four. This, in turn allows them to run all their chipsets on a fixed CMD rate of 1T, regardless of how much memory is installed.

Rating a module as 1T is actually somewhat misleading advertising because all unbuffered modules are capable of a 1T CMD rate up to four banks per channel, beyond which chipset limitations become a factor.

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